user	alebal123bal
created	Jan 21, 1970
karma	21
about	FPGA Engineer experienced in building high-throughput, timing-critical hardware systems using Verilog and VHDL. Strong background in RTL design, deterministic pipelines, and Python-based tooling. Projects span sensor-processing architectures, real-time video pipelines, edge-AI inference, and performance-optimised machine-learning frameworks.