- The solution is simple. In our universe we have to dump heat through at least one dimension. That is inefficient and leaves only 2 remaining dimensions for the chip, hence all our chips are 2d rectangles. Simply add one dimension so that you can either build 3d chip and dump heat in 4th dimension, or keep chip 2d but dump heat throughout 2 extra dimensions much more efficiently.
- Fantastic idea... Now I'm gonna start thinking about what dumping heat into a 4th dimension might mean realistically... We need the heat to leave without the chip getting in the way. If we can make chips that are transparent to IR, maybe they can radiate energy from their volume directly.
Going to keep thinking about this. Could adding an impossible dimension be Triz 41? Maybe when we get to Triz 42 we'll figure out how to stop fighting over meaningless stuff as a species.
Edit: It's actually just Triz 17(another dimension)
- Is't heat accumulation over time already dumping heat in the 4th dimension?
- Silicon is already transparent for IR. Visibly that's not enough to cool chips.
- Is emitting infrared light really enough to cool a chip? How do you ensure enough is emitted that the chip doesn't just both get hot and emit IR?
- In living beings things can be 3-dimensional, like a brain, because they are penetrated by a fine network of tubes through which fluid is circulated, taking the heat away.
This is likely to also be the only solution for truly 3D integrated circuits (i.e. of unlimited thickness), but it is very difficult to ensure that such a solution has high reliability, because at least for now it cannot be self-repairable, like living tissues, so the cooling network can become clogged or it can start leaking.
- Aka "porous circuits". - Red Dwarf 1988
- This does not scale, due to square/cube law (the energy is generated in a volume, but has to leave via surface -> the energy evacuated per surface area has to grow)
- It scales, because the surface of the network of tubes that fills the volume also grows with the volume, unlike the external surface that encloses that volume. When the volume is scaled, the tubes (i.e. capillaries) are not scaled in size, but they grow in number per a given fraction of the volume. So the scaled devices are not geometrically similar, thus the law of variation of the area per volume with scaling does not apply.
This is why a brain or a muscle can scale from a mite with a volume of one thousandth of cubic millimeter to a whale.
The scaling is not ideal because the smallest capillaries must be aggregated into vessels of increasing size, so some part of the volume becomes wasted, but still the ratio of area per volume does not decrease linearly, as in the case when the external surface is used for cooling.
The same technique is applied in many engineering domains. For instance, the maximum current for a power transistor depends on the perimeter of the source or emitter, not on the die area. Therefore, if one would scale a power transistor maintaining geometric similarity, the switched power per die area would drop quickly, leading to very high costs for the devices.
Instead of this, a bigger power transistor does not have bigger sources or emitters, but it has more of them, with the same size as in the smallest transistors, which keeps constant the power switched per die area.
- Capillaries cannot defeat the divergence theorem: If you have a volume where heat is produced but the temperature does not increase, the heat has to leave via the surface. It is true that the surface area available to diffusion can scale at any rate (eg. Menger sponge), but the heat still has to leave the volume via its boundary. In the case of capillaries, this is by convection which means that the product of coolant temperature differential and flow speed has to scale.
- Thanks, this is what I wanted to say, but perhaps I was a bit too terse.
Perhaps a good coolant with a good flow speed can gain you a decent constant factor versus a classical heat sink, but once the third dimension of your chip gets bigger, you will hit a barrier. Just do the math.
- But it does, at least to some degree: For the cpu (or brain) you want high density to minimize the latency between components. For the heat sink, you want high surface area, which you can actually do to some degree three-dimensionally, particularly when you have active cooling. Look at a typical heat sink with a fan attached to it -- it has some depth, because that depth allows more heat to be transferred to the air to it by increasing the surface area exposed to the air. Lungs do the same thing, and they do function as part of our cooling system. So if you have a way that the flow of the exchange medium is not limited by the external surface area of your heat exchanger (a fan, a pump, a diaphragm), you can go pretty far.
- It doesn't scale forever in the extra dimension but it does at least scale a hell of a lot better than just using the envelope of the volume or using a single flat layer.
- The issue is that we only have time as the 4th dimension, which just means the chips have to run slower to dissipate the heat over more time. ;)
- Elephants are 3D and really big. But they have really big ears too, to dissipate heat because as body mass grows at the power of 3, their skin only grows at the power of 2.
I am not sure where am I going with this, but it would be funny to have chips with big ears and a fake mustache.
- I think my massive noctua heat sink is basically that lol
- I mean, that's just radiators
- Maybe we can just dump heat into the time dimension and deal with it in the past or the future.
- Turn the chip into a loop or sphere? Allowing for continous computation till hot- then transfer over to neighbouring dark silicone.
- I am too stupid to know if this is really smart or really dumb.
- So we're doing really tiny cordwood construction now? https://en.wikipedia.org/wiki/Printed_circuit_board#Cordwood...
- Nifty link, I learned something new today. I know it's much more convenient building pcb's the way we do today, but maybe there are certain advantages we could get by exploring non-conventional layout strategies at the PCB level. I remember seeing some interesting applications with strategically milled PCB's to get flex on the PCB to fit it some specific confines.
- Also look into Mythic AI, and also the recent (ultimately tragic) story of the wurtzite ferroelectric device breakthrough at the University of Michigan.
- Heat is a huge problem?
Heat radiation elements must be designed as part of the structure?
Sophie Wilson has famously said how easy it is for active silicon to get hotter than a nuclear reactor.
- Heat is exactly why this is useful. A very large amount of power draw is due to the physical size of circuits. This monolithic 3D stacking should result in smaller wires for decreased parasitic capacitance. SRAM is probably the biggest winner in some respects. The paper suggests they can make SRAM smaller, and given most of a modern CPU die is SRAM I would be shocked if that wasn’t a huge thermal win alone, either by adding more cache or by reducing the size of the core or both.
I’d be interested to see if you couldn’t throw diamonds at the heat problem though. There was some recent work done suggesting diamond could help a lot with heat, but I’m unsure if it would work here.
- Yeah; without Dennard Scaling, cooling becomes an issue, they're useless to laptops, and you can only double or triple density vs a regular chip before they draw too much power for a home outlet.
- > Sophie Wilson has famously said how easy it is for active silicon to get hotter than a nuclear reactor.
The center of a fuel rod in a PWR reaches more than 1000 C.
Perhaps Wilson was talking about the thermal power/area of chips vs. the surface of fuel rods. I believe the former can exceed the latter.
- Poorly designed or managed chips can reach the point that hot spots in the silicon literally melt, which happens at ~1400C. Thermodynamics sitting on an insulator (relative to the metal portions of the chip at least) on very small scales is very weird and can reach wild spot temps.
That's why chip thermals is its own whole subfield of physical design.
- Sure, but the center of a PWR fuel rod reaches high temperature in normal operation. Uranium dioxide is not a great conductor of heat.
Chips have the advantage that the workings are right at the surface, mere microns from it. So the heat can easily get out. The power density in that thin surface layer can be very high. Perhaps similarly, the power density of a PV cell can be very high, if one just looks at the active layer where light is being absorbed. In CdTe this layer is < 1 micron thick. The energy delivered over the life of the cell per atom in this layer can approach that of nuclear reactions.
- I will add that if we're talking about abnormal operation, say in a reactor meltdown, uranium dioxide can reach its melting point, 2865 C.
Anyway, it's a promising comparison, since the core of a PWR can reach volumetric power density of ~100 MW/m^3 (and probably higher in naval reactors). Servers can potentially be made very compact.
- The amount of current that can be pushed through a thin silicon die is just wild.
- I think of that every time I watch my GPU hit 440W sustained power draw on a die that is ~23mm square.
Which comes out to be about 831kW per square meter and the cooling solution keeps it at 60-63C even under that load (while noticeably warming my office since it's effectively dumping the same as one bar on a two bar electric heater).
As a species, we got really good at engineering.
- > active silicon
This is not necessarily a functioning chip.
- Typically this is used to stack many layers of memory on top of one or two layers of compute.
- > Microelectronics manufacturing has been driven for the past 60 years by Moore’s law, which states that the density of transistors on a chip should double every two years. The electronics industry has adopted this principle as a production goal to increase the power and efficiency of computer processors. It has proven successful and steady for decades, but there are signs that the trend is starting to stall.
"Signs it's starting to stall"? Moore's 'law' has been dead for a decade at minimum at the literal interpretation, and for over two decades if observable performance is what you actually cared to measure. What does this even have to do with the research the article is about? It's not clear to me why the author felt the need to shoehorn this into the headline.
- Well, Mooress original statement coupled transistor density to cost. With the current RAM pricing, it looks to me like Moore's law is not only dead, but in fact reversed - the cost of a fixed density of DRAM cells double roughly every 12? Months.
- RAM price booms & busts have been a thing since at least the early 1980's, when Andy Grove got Intel out of the memory manufacturing business - because he didn't like the financial aspects, nor the sort of big competitors who were establishing themselves there.
- Especially since "restarting Moore's law" would be an even more badass headline, as long as you're exaggerating for clicks anyway.
- I disagree, as far as transistor density it's not completely dead. Looking at the following logarithmic graph there's an inflection point around 2005, it slowed down but it still looks like we're on an exponential growth path.
https://ourworldindata.org/cdn-cgi/imagedelivery/qLq-8BTgXU8...
- It feels odd that that graph includes some CPUs with integrated GPUs, but otherwise only focuses on CPU transistor count. I wonder what a graph of 'biggest/mean/median retail CPU + dedicated GPU combo transistor count' would look like - presumably the graph would be a decent amount steeper?
I definitely think counting GPU as part of the compute package makes sense given how much of modern computing is now delegated to it outside of just rendering.
- There's no cost on your graph, so you don't know what is the most economical package.
The fact that the width of the distribution became so much larger after that inflection is evidence against your point. Your graph points suggestively into Moore's law being dead.
(But we do know it died when fabs started making 3D transistors. No need to look at suggestions.)
- Mores law is talking density on a silicon wafers. When you start stacking layers or using larger chips it no longer applies.
- Which of the Moore's laws would that be? It seems people talk about Moore's law without actually specifying what the law says. Transistor per SQ mm? Transistor count in a chip overall? Transistors built in the world at all? General hand-wavy performance of compute?
You never know what the counterpart is saying when claiming it dead or alive and people seem to have _ wildly_ different concepts what it means.
The original quote seems to be: "The complexity for minimum component costs has increased at a rate of roughly a factor of two per year" - I think this held up pretty well.
Wikipedia says:
"Moore's law is the observation that the number of transistors in an integrated circuit (IC) doubles about every two years, with minimal increase in cost."
Notice nowhere any mention of area. It's more related to cost?
- The original use was in terms of transistors in an integrated circuit doubling every year at identical cost. That rate was revised down by Moore multiple times.
So it doesn’t have a firm definition, but ever larger and more expensive chips isn’t what it was referring to.
- “Moore’s Rule of Thumb” is a descriptor I read in a hard print magazine back when my phone had buttons and we all wore onions tied to our belts.
A critical insight for its time, but not quite a thermodynamic principle our great-grand kids will be able to verify on their fancy new modern phones that finally got buttons.
- Sounds similar to the idea huawei is talking about.
73 points by hhs 2 days ago | 46 comments